How to Use
Select graph:
- bw: Bisection width
- Partition: Balanced cut
- VLSI: Area bound
VLSI Connection
Thompson's theorem: VLSI area A(G) = Ω(bw²). Large bisection width → large chip area needed. Fundamental lower bound for circuit layout. Bisection width determines die size minimum.
Parallel Computing
Communication bottleneck in parallel algorithms: bisection width = max throughput of bisection cut. Large bw → better routing. Small bw → communication bottleneck. Drives network topology design.
Step-by-Step Instructions
- 1Select graph.
- 2Find balanced partition.
- 3Count crossing edges.
- 4Minimize cut.
- 5Apply VLSI/parallel.